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The encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM
address 0x83, AES_CTRL or the mirrored version with SRAM address 0x94,
AES_CTRL_MIRROR).
The AES module control registers are only accessible using SRAM read and write
accesses on address space 0x82 to 0x94. A configuration of the AES mode, providing
the data and the start of the operation can be combined within one SRAM access.
Notes:
1. No additional register access is required to operate the security block.
2. Access to the security block is not possible while the radio transceiver is
in SLEEP, or RESET state.
3. All configurations of the security module, the SRAM content and keys
are reset during RESET state.
11.1.3 Security Key Setup
The setup of the key is prepared by setting register bits AES_MODE = 1 (SRAM
address 0x83, AES_CTRL). Afterwards the 128-bit key must be written to SRAM
addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to combine the
setting of control register 0x83 (AES_CTRL) and the 128-bit key transfer using only one
SRAM access starting from address 0x83.
The address space for the 128-bit key and 128-bit data is identical from programming
point of view. However, both use different pages which are selected by register bit
AES_MODE before storing the data.
A read access to registers AES_KEY (0x84 – 0x93) returns the last round key of the
preceding security operation. After an ECB encryption operation, this is the key that is
required for the corresponding ECB decryption operation. However, the initial AES key,
written to the security module in advance of an AES run, see step one in Table 11-1 , is
not modified during an AES operation. This initial key is used for the next AES run even
it cannot be read from AES_KEY.
Note:
1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security
processing. The Atmel AT86RF232 provides this functionality as an
additional feature.
11.1.4 Security Operation Modes
11.1.4.1 Electronic Code Book (ECB)
ECB is the basic operating mode of the security module. After setting up the initial AES
key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) sets up ECB
mode. Register bit AES_DIR (SRAM address 0x83, AES_CTRL) selects the direction,
either encryption or decryption. The data to be processed has to be written to SRAM
addresses 0x84 through 0x93 (registers AES_STATE).
An example for a programming sequence is shown in Figure 11-1 . This example
assumes a suitable key has been loaded before.
A security operation can be started within one SRAM access by appending the start
command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI
sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83
(AES_CTRL).
126
AT86RF232
8321A – MCU Wireless – 10/11
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